An array of die, which may include integrated circuits and their components, are formed on and/or within a wafer during various semiconductor fabrication processes. At various stages during fabrication, it may be desirable to perform testing on the die to read information, write information, or otherwise gather information about the die and/or the components of the die. During testing, the wafer may be loaded into a prober that operates to sequentially align each die on the wafer with the test equipment. The test equipment may include a testhead that is positioned and locked proximate the prober in an optimum testing position. This positioning and locking operation is known as “docking” the testhead to the prober. For example, where the test environment includes a mounted probe card, the testhead is to be docked into position such that one or more contact points of the die may be aligned with one or more contact points on the probe card.
Typical manipulating and docking systems do not compensate for stack up variances associated with component interchangeability within the testhead, probe card, and prober. Rather, they rely on stack up tolerance control to ensure that the plane formed by the probe card's contact points is parallel to the plane of the die's contact points. Achieving and maintaining parallelism of these two planes by stack up control alone is impractical for systems that use vacuum to attach the probe card to the testhead. Planarity in vacuum attach systems is particularly vulnerable to stack up errors since the probe card's contact reference plane is primarily influenced by the reference plane of the testhead, its interfacing components, the prober, and the physical characteristics of the probe card itself.